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472-475. K. Chao, S. Nadeem, W. Lee, and C. Sodini, “A higher-order topology for interpolative modulation for oversampling A/D converters,” IEEE Transactions on Circuits and Systems, vol. 37, pp. 309-318, Mar. 1990. S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters, Theory, Design, and Simulation. New York: IEEE Press, 1997. P. Ju and D. Vallancourt, “Quantization noise reduction in multibit oversampling A/D convertors,” Electronics Letters, vol. 28, pp. 11621163, June 1992.

The register is also called the phase register. e. every cycles of a VCO pulse is swallowed. Therefore, the sawtooth-shaped phase error is also periodic with a period depending on K. The resulting AC component, superimposed on the wanted DC output of the phase detector, modulates the VCO frequency and large spurious components appear in the PLL output spectrum at multiples of even after filtering by the loop filter. Since the accumulator is in fact nothing more than a first-order modulator, theory can be applied to the fractional-N synthesizer (see Fig.

Setterberg, and A. 5GHz frequency synthesizer with settling and 2Mb/s closed loop modulation,” in ISSCC Dig. Tech. Papers, Feb. 2000, pp. 200-201. 26 [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] B. , May 2002, pp. 425-428. R. Ahola and K. Halonen, “A 2GHz fractional-N frequency synthesizer in CMOS,” in Proc. European Solid-State Circuits Conference, Sep. 2000, pp. 472-475. K. Chao, S. Nadeem, W. Lee, and C. Sodini, “A higher-order topology for interpolative modulation for oversampling A/D converters,” IEEE Transactions on Circuits and Systems, vol.

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